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FMS6400-1 Dual Channel Video Drivers with Integrated Filters and Composite Video Summer
June 2005
FMS6400-1 Dual Channel Video Drivers with Integrated Filters and Composite Video Summer
Features
5.0 MHz 5th order Y,C filters with composite summer Selectable for 0dB or 6dB gain 50dB stopband attenuation at 27MHz on Y, C and CV outputs No external frequency selection components or clocks AC-Coupled Inputs AC or DC-Coupled Outputs Continuous time low pass filters 0.4% / 0.4 differential gain/phase on Y,C and CV channels Integrated DC restore circuitry with low tilt Lead (Pb) Free SOIC-8 Package
Description
The FMS6400-1 is a dual Y/C 5th order Butterworth lowpass video filter optimized for minimum overshoot and flat group delay. The device also contains a summing circuit to generate filtered composite video. In a typical application, the Y and C input signals from DACs are AC coupled into the filters. Both channels have DC restore circuitry to clamp the DC input levels during video sync. The Y and C channels use separate feedback clamps. The clamp pulse is derived from the Y channel. All outputs are capable of driving 2Vpp, AC or DC coupled, into either a single or dual video load. A single video load consists of a series 75 impedance matching resistor connected to a terminated 75 line. This presents a total of 150 of loading to the part. A dual load would be two of these in parallel which would present a total of 75 to the part. The gain of the Y, C and CV signals can be selected for 0dB or 6dB with 1Vpp input levels. All video channels are clamped during sync to establish the appropriate output voltage reference levels.
Applications
Cable and Satellite set top boxes DVD players Personal Video Recorders (PVR) Video On Demand (VOD)
Block Diagrams
VCC 7 Sync Strip Reference and Timing
0 or 6dB
YIN
1
8
YOUT
gM
250mV +
S
+
6
CVOUT
gM
250mV
CIN
4
0 or 6dB
5
COUT
3 GND
2 ASEL
(c)2004 Fairchild Semiconductor Corporation
1
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FMS6400-1 Rev. 1A
FMS6400-1 Dual Channel Video Drivers with Integrated Filters and Composite Video Summer
Pin Configuration
Pin Assignments
Pin#
1
Pin
YIN
Type
Input
Description
Luminance (Luma) Input: In a typical system, this pin is connected to the Luma or composite video output pin from the external video encoder. Channel Gain Select. `0 '= 0dB, `1' = 6dB Must be tied to Ground Chrominance (Chroma) Input: In a typical system, this pin is connected to the Chroma output pin from the external video encoder. Filtered Chrominance Video Output from the CIN channel. Composite Video Output: This pin is the sum of YOUT and COUT . +5V supply Filtered Luminance Output from the YIN channel.
FAIRCHILD
YIN ASEL GND CIN
1 8
2
YOUT
ASEL GND CIN
Input Input Input
FMS6400-1
2 7
3
VCC CVOUT
4
8L SOIC
3 4 6 5
5
COUT
COUT CVOUT VCC YOUT
Output Output Input Output
6 7 8
Typical Application Diagram
FMS6400-1 may also be DC-Coupled 0.1F YIN 1 YIN YOUT 8 75 220F YOUT 75 FMS6400-1 ASEL CVOUT 6 220F To TV 75 0.1F CIN 220F CVOUT to VCR
User Sets to logic 0 or 1
2
75
4
75 CIN COUT 5 VCC GND 3 75
75 220F
5V 0.1F
7 10F
COUT 75
Figure 1. AC or DC-Coupled Application Diagram
2 FMS6400-1 Rev. 1A
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FMS6400-1 Dual Channel Video Drivers with Integrated Filters and Composite Video Summer
Absolute Maximum Ratings
Parameter
DC Supply Voltage Analog and Digital I/O Output Current Any One Channel, Do Not Exceed
Min.
-0.3 -0.3
Max.
6 Vcc + 0.3 40
Unit
V V mA
Note:
Functional operation under any of these conditions in NOT implied. Performance and reliability are guaranteed only if operating conditions are not exceeded.
Reliability Information
Parameter
Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Thermal Resistance (ThetaJA), JEDEC Standard Multi-Layer Test Boards, Still Air 115 -65
Min.
Typ.
Max.
150 150 300
Unit
C C C C/W
Recommended Operating Conditions
Parameter
Operating Temperature Range Supply Voltage Range
Min.
0 4.75
Typ.
5.0
Max.
70 5.25
Unit
C V
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FMS6400-1 Dual Channel Video Drivers with Integrated Filters and Composite Video Summer
DC Electrical Characteristics
Tc = 25C, Vcc = 5V, Vin = 1Vpp, ASEL = 1 (6dB gain), all inputs AC coupled with 0.1uF, all outputs AC coupled with 220uF into 150 loads, referenced to 400kHz; unless otherwise noted. Symbol
ICC Vi PSRR Supply
Parameter
Current1 No load Input Voltage Max Power Supply Rejection Ratio
Conditions
Min.
Typ.
50 1.4
Max
65
Units
mA Vpp dB
All channels, DC
50
AC Electrical Characteristics
Tc = 25C, Vcc = 5V, Vin = 1Vpp, ASEL = 1 (6dB gain), all inputs AC coupled with 0.1uF, all outputs AC coupled with 220uF into 150 loads, referenced to 400kHz; unless otherwise noted. Symbol
AV0dB AV6dB Csync Ysync CVsync TCLAMP fFLAT fC fSB dG dP THD XTALK SNR
Parameter
Channel Gain
1
Conditions
All Channels , ASEL = 0 All Channels , ASEL = 1 Sync present on YIN (after 6dB gain) Sync present on YIN (after 6dB gain) Sync present on YIN (after 6dB gain) All Channels All Channels All Channels at 27MHz All Channels All Channels VOUT = 1.4Vpp, 3.58MHz at 3.58MHz NTC-7 weighting, 4.2MHz LP, 100kHz HP All Channels All Channels at 3.58MHz at 1MHz f = 3.58MHz (ref to YIN at 400kHz) f = 3.58MHz (ref to YIN at 400kHz)
Min.
-0.25 5.75 0.8 0.2 0.2
Typ.
0 6.0 1.0 0.35 0.35 10 -0.05
Max
0.25 6.25 1.3 0.5 0.5
Units
dB dB V V V ms dB MHz dB % deg % dB dB dB ns ns ns
Channel Gain1 COUT Output Level (during sync)1 YOUT Output Level (during sync)1 CVOUT Output Level (during Gain Flatness to 2.4MHz -3dB Bandwidth1 Stopband Attenuation1 Differential Gain Differential Phase Output Distortion Crosstalk Signal-to-Noise Ratio Y,C Channel Signal-to-Noise Ratio CV Channel sync)1
Clamp Response Time (Y channel) Settled to within 10mV
4.1 37
5.1 52 0.4 0.4 0.3 -45 75 70 136 10 0
tpd GD tSKEW tCLGCV tCLDCV
Propogation Delay Group Delay Deviation Skew Between YOUT and COUT Chroma-Luma Gain CVOUT1 Chroma-Luma Delay CVOUT
94
100 10
104
% ns
Notes: 1. 100% tested at 25C
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FMS6400-1 Dual Channel Video Drivers with Integrated Filters and Composite Video Summer
Applications Information
Functional Description
This product is a two channel monolithic continuous time video filter designed for reconstructing the luminance and chrominance signals from an S-Video D/A source. Composite video output is generated by summing the Y and C outputs. The chip is designed to have AC coupled inputs and will work equally well with either AC or DC coupled outputs. The reconstruction filters provide a 5th order Butterworth response with group delay equalization. This provides a maximally flat response in terms of delay and amplitude. Each of the three outputs is capable of driving 2Vpp into a 75 load. All channels are clamped during the sync interval to set the appropriate minimum output dc level. With this operation the effective input time constant is greatly reduced, which allows for the use of small low cost coupling capacitors. The net effect is that the input will settle to 10mV in 10ms for any DC shifts present in the input video signal. In most applications the input coupling capacitors are 0.1F. The Y and C inputs typically sink 1A of current during active video, which normally tilts a horizontal line by 2mV at the Y output. During sync, the clamp restores this leakage current by sourcing an average of 20A over the clamp interval. Any change in the coupling capacitor values will affect the amount of tilt per line. Any reduction in tilt will come with an increase in settling time.
Layout Considerations
General layout and supply bypassing play major roles in high frequency performance and thermal characteristics. Fairchild offers a demonstration board, FMS6400DEMO, to use as a guide for layout and to aid in device testing and characterization. The FMS6400DEMO is a 4-layer board with a full power and ground plane. For optimum results, follow the steps below as a basis for high frequency layout: * Include 10F and 0.1F ceramic bypass capacitors * Place the 10F capacitor within 0.75 inches of the power pin * Place the 0.1F capacitor within 0.1 inches of the power pin * If using DC-coupled outputs, use a large ground plane to help dissipate heat * Minimize all trace lengths to reduce series inductances
Luminance (Y) I/O
The typical luma input is driven by either a low impedance source of 1Vpp or the output of a 75 terminated line driven by the output of a current DAC. In either case, the input must be capacitively coupled to allow the sync-detect and DC restore circuitry to operate properly. All outputs are capable of driving 2Vpp, AC or DC coupled, into either a single or dual video load. A single video load consists of a series 75 impedance matching resistor connected to a terminated 75 line, this presents a total of 150 of loading to the part. A dual load would be two of these in parallel which would present a total of 75 to the part. Channel gain of 0dB on all channels can be selected by tying pin 2 to ground. Channel gain of 6dB on all channels can be selected by tying pin 2 to VCC. Both gain settings assume standard input video levels of 1Vpp.
Chrominance (C) I/O
The chrominance input can be driven in the same manner as the luminance input but is typically only a 0.7Vpp signal. Since the chrominance signal doesn't contain any DC content, the output signal can be AC coupled using as small as a 0.1F capacitor if DC coupling is not desired.
Composite Video (CV) Output
The composite video output driver is same as the other outputs.
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FMS6400-1 Dual Channel Video Drivers with Integrated Filters and Composite Video Summer
Mechanical Dimensions
6
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FMS6400-1 Rev. 1A
FMS6400-1 Dual Channel Video Drivers with Integrated Filters and Composite Video Summer
Ordering Information
Model FMS6400-1 FMS6400-1 Part Number FMS6400CS1 FMS6400CS1X Lead Free Yes Yes Package SOIC-8 SOIC-8 Container Rail Reel Pack Qty 95 2500
Temperature range for all parts: 0C to 70C.
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FMS6400-1 Dual Channel Video Drivers with Integrated Filters and Composite Video Summer
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. I7
8 FMS6400-1 Rev. 1A
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